This invention relates to integrated circuits, and more particularly to differential buffer chips.
Memory modules are widely used in electronic systems such as personal computers. Various standards are used, such as those by the Joint Electronic Device Engineering Council (JEDEC). Some JEDEC standards use double-data-rate (DDR) dynamic-random-access memory (DRAM) chips on modules known as dual-inline-memory-modules (DIMMs). Differential input signals are used for faster signaling.
Very high-speed buffer chips are needed for interfacing with the DDR DRAM""s. Each data line, and perhaps some address or control signals are buffered. Bi-directional data lines can be supported by using two uni-directional data-buffer slices in parallel but in reverse directions.
FIG. 1 shows a bit-slice for a data buffer chip that interfaces with DDR DRAMs. Data input D(N) is one of 25 or so data lines input to a buffer chip. Data input D(N) is compared to a reference voltage Vref by differential buffer 16, then muxed by mux 22 before being applied to the D-input of flip-flop 20. The Q(N) output of flip-flop 20 is a latched data bit that can be applied to one of the DDR DRAM""s data inputs.
Vref is a reference voltage such as Vcc/2. Differential buffers 12, 14 also receive Vref. Differential buffer 12 compares data strobe input DCS to Vref while differential buffer 14 compares chip-select input CSR to Vref. NAND gate 24 combines the outputs of differential buffers 12, 14 and drives the control input to mux 22 through inverter 18.
When both DCS and CSR are high (above Vref), mux 22 selects the upper input, recycling the Q(N) output back to the D(N) input of flip-flop 20. When either of DCS or CSR pulse low, below Vref, mux 22 selects its lower input, and the data input D(N) is latched into flip-flop 20 on the next clock edge.
Clock buffer 26 receives a differential clock ICK and ICKB, and generates a clock edge to flip-flop 20 when the differential clock signals cross-over. Reset signal RST can be applied to differential buffers 12, 14, 16, clock buffer 26, and flip-flop 20.
While such a data buffer is useful, a propagation delay occurs for the data through mux 22. This delay tends to increase the data setup time, the amount of time that data input D(N) must arrive before the clock edge of ICK, ICKB to be safely latched into flip-flop 20. Since a tight setup time is specified by the JEDEC standard, the data-path delay may have to be reduced, such as by using a high-speed differential buffer 16. However, increasing the speed of differential buffer 16 requires a large current, which increases power consumption. Since there can be as many as 25 bit slices such as shown in FIG. 1 in a buffer chip, a large overall power consumption can occur. Such large power consumptions are undesirable.
What is desired is a buffer chip with lower power dissipation. A faster data input path to the flip-flop is desirable without relying on large-current differential input buffers.